Supervisor

Suitable for

Abstract

Prerequisites:  None

 

Most modern processors implement data-level parallelism using sets of single instruction multiple data (SIMD) instructions that operate on dedicated 128, 256 and 512-bit registers. By contrast, the RISC-V instruction set architecture proposes a vector extension which is much closer in design to that first used in the Cray-1 supercomputer. This extension incorporates hardware level dynamic types to avoid the large number of SIMD instructions that older implementations typically require, and uses dedicated vector registers whose length can change between different implementations. This flexible design allows identical code to run on processors whose vector registers have different lengths.

In this project, you will explore the design of the vector extension through simulation. You will simulate the vector extension in software, developing a deep understanding of the instruction set, and then use this simulation to identify applications where vector extensions offer significant benefits over conventional SIMD instructions. As a stretch goal, you will implement the vector instruction in Verilog on an FPGA to realise a hardware implementation of a RISC-V processor capable of executing vector operations.