With computers penetrating every day life it becomes all the more important to secure devices from malicious users. Capability Hardware Enhanced RISC Instructions (CHERI) architecture developed by SRI International and the University of Cambridge is an architecture-neutral capability-based protection model which offers fine-grained memory protection and scalable software compartmentalization. CHERI is designed to support incremental adoption within current security-critical, C- and C++-language Trusted Computing Bases (TCBs) like kernels, key system libraries, and language runtimes. Efforts are on to port legacy system softwares to run on CHERI enabled devices. My current effort is towards verifying such newly ported systems.